When analog data values are inputted to a PLC, an analog input unit (an A/D converter) that converts an inputted analog data value into a digital value is used. Generally, a sampling period of A/D conversion of the analog input unit that converts an inputted analog data value into a digital value is not synchronous with a control period (a scanning time) of a CPU unit that controls the entire PLC, and the sampling period is usually faster. Therefore, when the analog input unit logs an A/D conversion value, it is difficult to log all A/D conversion values in the CPU unit without fail.
As a method of logging all A/D conversion values without fail, there is a method of performing a logging process in an analog input unit. However, in order to refer to collected data, the data needs to be read into a CPU unit after logging is completed. Because this reading process conventionally has required a dedicated communication process to be performed for many times, so that this process is laborious.
To solve this problem, there has been proposed a technique of storing A/D conversion values in a shared memory serving as a memory area that can be always accessed by a CPU unit without requiring any dedicated communication process (see, for example, Patent Document 1). Further, there has been proposed a technique of collecting data in a ring buffer manner as a method of collecting successive data (see, for example, Patent Document 2). Furthermore, there has been proposed a technique of collecting data in a shared memory in a ring buffer manner (see, for example, Patent Document 3).    Patent Document 1: Japanese Patent Application Laid-open No. H8-69355    Patent Document 2: Japanese Patent Application Laid-open No. 2008-20392    Patent Document 3: Japanese Patent Application Laid-open No. 2007-233593